The present invention relates in general to semiconductor device fabrication methods and resulting structures. More specifically, the present invention relates to optimized gate stack fabrication methods and resulting structures for field effect transistors (FETs).
Semiconductor devices include a gate stack formed atop the channel region of the device. Either a gate-first or gate-last fabrication technique is performed to form the gate stack. A gate-last technique, also referred to as a replacement metal gate (RMG) process, includes first forming a sacrificial gate (i.e., dummy gate) atop the channel region, and then, as one of the final fabrication processes, replacing the dummy gate with a metal gate forming a pair of spacers on sidewalls of the sacrificial gate.